1. Field of the Invention
This invention relates to a signal reproducing apparatus and more particularly to an apparatus such as a digital VTR or the like which is arranged to be capable of varying its reproducing speed.
2. Description of Related Art
Known apparatuses of the kind mentioned above include VTRs which record and/or reproduce video signals on or from magnetic tapes by using rotary heads.
FIG. 1 shows the arrangement of a VTR of the above-stated kind. Referring to FIG. 1, magnetic heads 3a and 3b are mounted on a rotary drum 2 which is disposed in the neighborhood of a magnetic tape 1. A drum motor 2A is arranged to rotate the rotary drum 2 to cause the magnetic heads 3a and 3b to obliquely scan the surface of the magnetic tape 1 one after another.
A digital VTR which is arranged to record and/or reproduce a digital signal with rotary heads as mentioned above is next described as follows. FIG. 2 shows in a block diagram and by way of example the arrangement of the digital VTR using the rotary heads. Referring to FIG. 2, head amplifiers 4a and 4b are arranged to amplify signals reproduced respectively by the magnetic heads 3a and 3b. An electronic switch 5 is arranged to perform a switch-over action on the outputs of the head amplifiers 4a and 4b. A reproduction equalizer 6 is composed of an LC network having a predetermined frequency characteristic or the like. A data detecting circuit 7 is arranged to shape the waveform of an analog signal outputted from the reproduction equalizer 6 and to convert it again into the form of digital data. A D-flip-flop 8 is arranged to latch the digital data.
A PLL (phase-locked loop) circuit 9 is arranged to generate a clock signal which is phase-locked to the output, i.e., a reproduced digital signal, of the data detecting circuit 7 and to apply the clock signal to the D-flip-flop 8 and other subsequent circuits. Reference numeral 10 denotes a demodulator. An error correction decoding circuit 11 is arranged to make error correction by detecting any error included in the reproduced data. A reproduced signal processing circuit 12 is arranged to carry out a signal processing action on the reproduced signal which has been block-coded by DCT and compressed in amount of information. The signal processing action is carried out reversely to a signal processing action performed in recording, in such a way as to bring the reproduced digital signal back to its original form by expanding the amount of information. Reference numeral 13 denotes a D/A converter and reference numeral 14 an output terminal.
The digital VTR operates as follows. When the rotary drum 2 is rotated by the drum motor 2A, the magnetic heads 3a and 3b alternately read out recorded signals from the magnetic tape 1 on which tracks "a" and "b" are alternately recorded in a pattern as shown in FIG. 3. The reproduced signals which are read out in a minute state are amplified by the head amplifiers 4a and 4b to an extent between 50 and 60 dB. The outputs of the head amplifiers 4a and 4b are selected and combined into one signal through the electronic switch 5. The signal thus obtained has losses of varied kinds caused through the tape-head system. These losses are corrected by an equalizing action of the reproduction equalizer 6 which has such a frequency characteristic that emphasizes the low and high frequency bands of the signal.
The signal outputted from the reproduction equalizer 6 is supplied to the data detecting circuit 7 to be made into digital data by using a comparator or the like which selects a threshold level near a midpoint. The PLL circuit 9 generates a clock signal which is phase-locked to the reproduced digital data. The D-flip-flop 8 latches the reproduced digital data by using the clock signal.
The demodulator 10 demodulates the output of the D-flip-flop 8. The error correction decoding circuit 11 makes error correction. The reproduced signal processing circuit 12 performs a signal processing action in a manner which is almost reverse to a signal processing action performed in recording. The signal thus processed is supplied to the D/A converter 13. The D/A converter 13 D/A-converts the signal into a reproduced video signal, which is obtained at the output terminal 14.
The PLL circuit 9 is arranged and operates as follows. Referring to FIGS. 4 and 5, the PLL circuit 9 includes a phase comparator 15, a loop filter 16 and a voltage-controlled oscillator (hereinafter referred to as VCO) 17. The output of the data detecting circuit 7 is applied to one of the two input terminals of the phase comparator 15. A clock signal outputted from the VCO 17 is applied to the other input terminal of the phase comparator 15. The phase detecting characteristic of the phase comparator 15 is as follows. As shown in FIG. 5, when the phase of a second input signal advances with respect to a first input signal, the voltage of the output of the phase comparator 15 becomes larger.
When the signal phase of the reproduced digital data is caused to vary by unevenness of the rotation of the rotary drum 2 or by elongation or shrinkage of the magnetic tape 1, a phase difference between the clock signal and the reproduced digital data is detected by the phase comparator 15. Negative feedback of the result of detection is made to the VCO 17 through the loop filter 16 to use the result of detection for control over the oscillation frequency of the VCO 17, so that the clock signal can be phase-locked to the reproduced digital data by the negative feedback action.
With the digital VTR arranged as described above, in a special reproduction mode such as a high speed search mode, the magnetic heads 3a and 3b are caused to perform scanning by straddling several recording tracks in a manner as indicated by broken lines in FIG. 6. As a result, the length of scanning per turn of the rotary drum 2 increases to increase a speed at which the magnetic heads 3a and 3b scan the magnetic tape 1, i.e., the so-called relative speed.
To cope with such a state, it is conceivable to somewhat mitigate changes taking place in the relative speed by applying, to the servo circuit of the drum motor 2A, a roughly predetermined value corresponding to the multiple speed value of the high speed search.
However, according to this method, it is hardly possible to sufficiently mitigate the changes of the relative speed in the case of a high speed search to be made, for example, at a centuple-fold speed. In the event of such a high speed search, therefore, the PLL circuit 9 becomes incapable of carrying out a phase pull-in action, following the frequency variations of the reproduced data, and then all the reproduced data might become erroneous.